1. Field
This disclosure relates generally to a processor subsystem and, more specifically, to techniques for operating a processor subsystem.
2. Related Art
In battery-powered systems, such as handheld computers and cellular telephones, in order to reduce power consumption and increase battery-life, designers have frequently designed the systems to enter a low-power (or deep sleep) state during periods of inactivity. In the low-power state, power has usually been removed from one or more portions of an integrated circuit (IC) that have relatively high leakage currents in order to increase battery-life. However, in such systems, a current state of a processor core (processor) has not usually been saved prior to causing the processor to enter the low-power state. As such, when an activity occurs (as, for example, indicated by an interrupt) that requires powering-up the systems, the systems have re-started in a boot-up state that is not indicative of a last state of the processor prior to entering the low-power state.
Typically, computer systems perform computational operations on data values stored in a set of processor registers. As each function within a program usually operates on its own set of registers, an active register set of a processor may change when a current function changes, e.g., during a function call operation or a function return operation. Usually, the function change involves saving a current register set to memory during a function call operation to make room for a new register set for the new function, and subsequently restoring the current register set from the memory during a corresponding function return operation. The process of saving and restoring register sets to memory can significantly degrade computer system performance. In some processor implementations, a physical register file is partitioned into an architectural register file and a working register file containing rename registers. In a rename stage, destination registers are allocated rename registers and the rename registers are copied back to the architectural register at retirement. In alternative implementations, the physical register file is not partitioned and a retire unit does not have to copy a working register to an architectural register.
In either implementation, during a save operation, the processor has usually allocated an entire window, even if the function generates only a subset of live registers in the window. In this case, a relatively large portion of the physical register file may contain dead or unused registers. These dead registers are usually recovered by a subsequent restore instruction. However, in an intervening period, the window may potentially be spilled/filled multiple times leading to decreased processor performance, as unused registers are spilled/filled. U.S. Pat. No. 7,127,592 discloses a technique in which dead registers are not included in fill/spill operations to decrease fill/spill operation overhead and increase processor performance. Similarly, U.S. Patent Application Publication No. 2006/0149940 discloses another technique for performing a save and restore on a context switch. Likewise, U.S. Patent Application Publication No. 2004/0215941 discloses yet another technique for handling window fill/spill operations using helper instructions. While the above-identified references (i.e., patent and publications) address increasing efficiency of save/restore operations during a context switch, the references do not address save/restore operations of a processor subsystem during a power-down or power-up sequence.
What is needed is a technique to save a correct processor state during a power-down sequence of a processor subsystem. It would also be desirable for the technique to restore the correct processor state during a subsequent power-up sequence of the processor subsystem.